The present invention relates to a structure and a method for forming a wafer comprising semiconductor and dielectric material. More specifically, this invention relates to a structure and method in which a dielectric layer is deposited at a specified thickness above a semiconductor layer.
Previously known structures referred to as inter-layer dielectric (ILD) and inter-metal dielectric (IMD) comprise a layer of dielectric deposited on top of another layer such as metal. The dielectric is typically overfilled to twice the dielectric thickness that is required in the final structure. Chemical mechanical planarization (CMP) is then performed to reduce the thickness of the dielectric layer to the required level. For example, a 20,000 angstroms thick layer of dielectric may be deposited on top of a 6,000 angstroms thick layer of metal. CMP may then be performed to reduce the thickness of the dielectric layer to 10,000 angstroms.
Another previously know technique referred to as shallow trench isolation (STI) involves depositing a dielectric layer in a trench. The dielectric layer is typically overfilled by 100% of the depth of the trench. For example, for a trench that is 3,000 angstroms deep, a dielectric layer may be formed on top of the trench that is 6,000 angstroms thick. CMP may then be performed to reduce the thickness of the dielectric layer to the desired thickness (e.g., 3,000 angstroms).
However, the thickness of deposited layers such as dielectric are often non-uniform across a wafer due to irregularities in the deposition process. Non-uniformities increase as more material is deposited to increase the thickness of the layer. Also, the CMP process may introduce additional non-uniformities into the thickness of deposited layers across the surface of a wafer. Non-uniformities due to the CMP process increase as more CMP is performed over a longer period of time.
In previously known inter-metal dielectric (IMD) layers, CMP is performed on the deposited inter-metal dielectric layer. Substantial dielectric remains above a metal layer following CMP to minimize capacitance. The surface of the underlying metal layer is not planarized. It can be assumed that the thickness of the metal layer is fixed across the wafer, because CMP has not been performed directly upon the metal layer. The thickness of the inter-metal dielectric layer can be measured using reflectance spectroscopy.
It would therefore be desirable to provide a process and structure comprising a wafer with a dielectric layer and a semiconductor layer in which the deposition of dielectric and chemical mechanical planarization on the dielectric layer are reduced.
It would also be desirable to provide a process and structure comprising a wafer with a dielectric layer and a semiconductor layer in which non-uniformities in layer thickness across the wafer are reduced.
It is an object of the present invention to provide a process and structure comprising a wafer with a dielectric layer and a semiconductor layer in which the deposition of dielectric and chemical mechanical planarization on the dielectric layer are reduced.
It is also an object of the present invention to provide a process and structure comprising a wafer with a dielectric layer and a semiconductor layer in which non-uniformities in layer thickness across the wafer are reduced.
Wafers of the present invention comprise a semiconductor layer and a dielectric layer deposited on top of the semiconductor layer. The semiconductor layer is patterned and etched to form semiconductor regions. The dielectric layer is formed on top of and in between the semiconductor regions. Chemical mechanical planarization (CMP) is then performed to remove a portion of the dielectric layer, exposing a predetermined amount of the semiconductor regions. The deposition of dielectric and the amount of CMP necessary to expose all of these semiconductor regions are both reduced, because the dielectric is targeted to fill up gaps in between the semiconductor regions only up to the upper surface of the semiconductor regions. This technique reduces non-uniformities in the thickness of the dielectric and semiconductor layers across the wafer.
The thickness of the dielectric or semiconductor layer deposited on polish monitors located at the edges of each die may be monitored to determine when enough CMP has been performed to expose all of the semiconductor regions. The thickness of the dielectric gap fill regions may be determined by using reflectance spectroscopy or other techniques, even when CMP has been performed on the semiconductor layer below. Dummy arrays may be formed next to active arrays in a memory device with rail stacks to further reduce variations in the thickness of the layers caused by CMP.